A Low Jitter Phase Locked Loop for High Speed Serial Interfaces
نویسندگان
چکیده
This paper presents a new circuit for clock generation. A new phase frequency detector is designed in 130nm CMOS process technology. The phase locked loop is designed to meet the 10BaseKR wire line communication standards. All the circuits are designed in current mode logic for high speed operation. The designed circuit dissipates mW. The voltage controlled oscillator has phase noise of -182. 2dBc/Hz at 1 MHz offset from center frequency. The designed phase locked loop has rms phase jitter of 44. 17fs. Refer ences
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